1. Technical Field
The present invention relates to a semiconductor device and method of manufacturing the same, and particularly to a semiconductor device provided with a plurality of electrodes formed on a semiconductor substrate and an insulating film for insulating each electrode. The insulating film protects each electrode from etching at the time of forming contact holes in a self aligned manner at small narrow spaces between adjoining electrodes.
2. Related Art
Recently, the integration density of semiconductors has improved rapidly, and accompanying this rapid increase one technical demand that has arisen is making the various patterns forming the semiconductor finer in detail. For example, in a semiconductor memory device it is necessary to form cell structures that are extremely small, for instance having half micron or quarter micron units. In order to satisfy such demands it is necessary to reduce the distance between each gate (electrode) formed on a semiconductor substrate, and further, when contact holes are formed between each gate it is necessary to make these contact holes finer. Accordingly, using only conventional photolithography techniques that have been used up to now, positioning accuracy of contact holes is limited, and it is difficult to make ultra-fine contact holes. Recently, a self aligning contact structure (hereinafter referred to as "SAC structure") has been adopted in semiconductor devices, and a technique has been provided for forming ultra-fine contact holes in the small narrow spaces between each gate, without controlling positional accuracy when using photo lithography.
Now, referring to FIG. 8, a semiconductor device adopting a general SAC structure will be described. As shown in the drawing, this semiconductor device has gates 14 of polysilicon formed on a semiconductor silicon substrate (hereinafter called a silicon substrate) 10, via gate dielectric films 12, and offset CVD oxidation films (hereinafter called offset oxidation films) 18 of silicon oxide (SiO.sub.2) are formed on these gates 14. Etching stopper nitride films 20 of silicon nitride (Si.sub.3 N.sub.4) are formed on the offset oxidation films 18. Integrally formed side walls 22 of silicon nitride, the same material as the etching stopper nitride films 20, are formed from a side surface of the etching stopper nitride films 20, via the side surfaces of the offset oxidation films 18 to side surfaces of the gates 14. Similarly to the etching stopper nitride films 20, the side walls 22 also function as etching stopper films. Inter layer insulation films 16 are also formed covering the gates 14.
When making contact holes 24, the etching stopper nitride film 20 as described above and the side walls 22 function as etching stopper layers, and protect against etching of the gates 14. Inter layer insulation films penetrate between the gates 14 in a self aligning manner, and the contact holes 24 are formed communicating with the silicon substrate 10.
In order to reduce the distance between each gate 14, it is necessary to make the cross sectional width of the side walls 22 formed on the side surfaces of the gates 14 relatively narrow. However, with the nature of the silicon nitride constituting the side walls 22, if the cross sectional width of the side walls 22 is made, for example, 50 nm or less, the insulation property will be lowered, and it will be easy for so called leakage current to flow between the gates 14 and contact portions formed in the contact holes 24. As a result, limitations naturally arise with reducing the cross sectional width of the side walls 22, and it is difficult to further reduce the distance between each gate 14.